Skip to content

[i2c, dv] I2C V1 sign-off #616

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
tchilikov-semify merged 1 commit into from
Sep 30, 2026
Merged

[i2c, dv] I2C V1 sign-off #616

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
50 changes: 45 additions & 5 deletions doc/proj/i2c.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,12 @@
The I2C in Mocha is imported from OpenTitan.
The documentation for the hardware IP block is located [in the vendored HW directory tree][block doc].
The block can be programmed in both controller and target modes.
It supports:
* standard, fast, and fast-plus speed modes
* 7-bit target address
* all the mandatory features listed for controllers in [Table 2: I2C specification Rev 6][]
* multi-controller features such as bus arbitration and controller-controller clock synchronization
* clock stretching in both controller and target modes.
`InputDelayCycles` is parameterized to zero and the RAM ports are configured to the single port package default.
The [vendor patch][patch] only fixes DV paths and the default simulator; no RTL is modified.

Expand Down Expand Up @@ -41,7 +47,26 @@ This sign-off is based on commit [8ac5ce9][d1-commit].

### V1

*Not yet started - see [stages.md][verification stages].*
All checklist items refer to the [V1 verification sign-off checklist][V1 checklist].
This sign-off is based on commit [`8ac5ce9`][v1-commit].

| Type | Item | Status | Note/Collaterals |
|---------------|------------------------------------|--------|------------------|
| Documentation | DV_DOC_DRAFT_COMPLETED | Done | [I2C DV document][] describes the goals, testbench architecture, stimulus, coverage, and checking strategy |
| Documentation | TESTPLAN_COMPLETED | Done | [I2C testplan][] defines the V1 smoke test and post-V1 functional, error, performance and stress testpoints |
| Testbench | TB_TOP_CREATED | Done | [tb.sv][] instantiates clock and reset, TileLink, I2C, and interrupt interfaces along with the I2C DUT |
| Testbench | PRELIMINARY_ASSERTION_CHECKS_ADDED | Done | [i2c_bind.sv][] binds the TLUL protocol and CSR assertions; the I2C RTL checks that outputs are known after reset |
| Integration | PRE_VERIFIED_SUB_MODULES_V1 | Waived | I2C and its primitive submodules are vendored from OpenTitan, where I2C reached [OpenTitan V2S stage sign-off][]; <br/> Mocha applies no functional changes |
| Review | DESIGN_SPEC_REVIEWED | Waived | The specification was reviewed through the OpenTitan sign-off process and the block was imported without functional <br/> changes |
| Review | TESTPLAN_REVIEWED | Done | The vendored [OpenTitan I2C checklist][] records the testplan review as complete |
| Review | STD_TEST_CATEGORIES_PLANNED | Done | Error scenarios, performance, overflow, timeout, glitch, and stress tests are covered in the [I2C testplan][]; <br/> security bus-integrity testing is currently out of scope for Mocha; power and debug are N/A |
| Simulation | SIM_TB_ENV_CREATED | Done | CIP-based UVM environment with I2C agent and scoreboard |
| Tests | SIM_SMOKE_TEST_PASSING | Done | `i2c_host_smoke` and `i2c_target_smoke`: 50/50 each passed with Xcelium on September 30, 2026 at commit `8ac5ce9` |
| Regression | SIM_SMOKE_REGRESSION_SETUP | Done | `smoke` regression in `i2c_sim_cfg.hjson` selects `i2c_host_smoke`; the aggregate Mocha config imports the I2C <br/> simulation config |
| Regression | SIM_NIGHTLY_REGRESSION_SETUP | Done | I2C is included in `mocha_sim_cfgs.hjson`; results are published on the [COSMIC reports dashboard][] |
| Coverage | SIM_COVERAGE_MODEL_ADDED | Done | I2C interface coverage is in `i2c_agent_cov.sv`; block-level coverage is in `i2c_env_cov.sv` |
| Tests | FPV_MAIN_ASSERTIONS_PROVEN | N/A | This V1 sign-off uses simulation; TLUL and CSR assertions are enabled in the simulation testbench |
| Regression | FPV_REGRESSION_SETUP | N/A | No I2C FPV regression is configured in Mocha |

### V2

Expand All @@ -51,15 +76,30 @@ This sign-off is based on commit [8ac5ce9][d1-commit].

*Checklist to be defined - see [stages.md][verification stages].*

[block doc]: ../../hw/vendor/lowrisc_ip/ip/i2c/README.md
<!-- External references -->
[Table 2: I2C specification Rev 6]: https://assets.nexperia.com/documents/user-manual/UM10204.pdf
[COSMIC reports dashboard]: https://dashboard.reports.lowrisc.org/cosmic/mocha/dashboard.html
Comment thread
tchilikov-semify marked this conversation as resolved.
[OpenTitan hash]: https://github.com/lowRISC/opentitan/tree/bf4a2b24e41742151cfce9c4041e959a3ba76ca3
[OpenTitan I2C checklist]: ../../hw/vendor/lowrisc_ip/ip/i2c/doc/checklist.md
[OpenTitan V2S stage sign-off]: https://github.com/lowRISC/opentitan/pull/24011

<!-- Stages and checklists -->
[stages]: stages.md
[missing asserts]: https://github.com/lowRISC/mocha/issues/708
[design stages]: stages.md#hardware-ip-block-design-stages
[verification stages]: stages.md#hardware-ip-block-verification-stages
[OpenTitan hash]: https://github.com/lowRISC/opentitan/tree/bf4a2b24e41742151cfce9c4041e959a3ba76ca3
[D1 checklist]: stages.md#d1-design-sign-off-checklist
[V1 checklist]: stages.md#v1-verification-sign-off-checklist

<!-- Commit anchors -->
[d1-commit]: https://github.com/lowRISC/mocha/commit/8ac5ce9d1e2af59bc12b834f7870e5a797a824a1
[v1-commit]: https://github.com/lowRISC/mocha/commit/8ac5ce9d1e2af59bc12b834f7870e5a797a824a1

<!-- Local file references -->
[block doc]: ../../hw/vendor/lowrisc_ip/ip/i2c/README.md
[registers]: ../../hw/vendor/lowrisc_ip/ip/i2c/doc/registers.md
[output asserts]: https://github.com/lowRISC/mocha/blob/8ac5ce9d1e2af59bc12b834f7870e5a797a824a1/hw/vendor/lowrisc_ip/ip/i2c/rtl/i2c.sv#L157-L181
[ot checklist]: ../../hw/vendor/lowrisc_ip/ip/i2c/doc/checklist.md
[patch]: ../../hw/vendor/patches/lowrisc_ip/i2c/0001-Fix-Paths-and-Tool.patch
[I2C DV document]: ../../hw/vendor/lowrisc_ip/ip/i2c/dv/README.md
[I2C testplan]: ../../hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson
[tb.sv]: ../../hw/vendor/lowrisc_ip/ip/i2c/dv/tb/tb.sv
[i2c_bind.sv]: ../../hw/vendor/lowrisc_ip/ip/i2c/dv/sva/i2c_bind.sv
2 changes: 1 addition & 1 deletion doc/proj/stages.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ This table shows the current design and verification stage for each block in Moc
| [Entropy source][] | D1 | V0 |
| [GPIO][] | D1 | V1 |
| [KMAC][] | D1 | V0 |
| [I2C][] | D1 | V0 |
| [I2C][] | D1 | V1 |
| [Mailbox][] | D1 | V0 |
| [PLIC][] | D1 | V0 |
| [Power manager][] | D1 | V0 |
Expand Down