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Fix crashes in &blut, exact, speedup, and write_verilog #570

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Merged
aletempiac merged 1 commit into from
Sep 25, 2026
+14 −3
Merged

Fix crashes in &blut, exact, speedup, and write_verilog #570

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6 changes: 5 additions & 1 deletion src/base/abci/abc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -10102,13 +10102,17 @@ int Abc_CommandExact( Abc_Frame_t * pAbc, int argc, char ** argv )
while ( true ) {
if ( *p2 == ',' )
{
if ( nVars >= 8 )
goto usage;
*p2 = '\0';
pArrTimeProfile[nVars++] = atoi( p1 );
*p2++ = ',';
p1 = p2;
}
else if ( *p2 == '\0' )
{
if ( nVars >= 8 )
goto usage;
pArrTimeProfile[nVars++] = atoi( p1 );
break;
}
Expand Down Expand Up @@ -40500,7 +40504,7 @@ int Abc_CommandAbc9BalanceLut( Abc_Frame_t * pAbc, int argc, char ** argv )
}
nLutSize = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
if ( nLutSize < 0 )
if ( nLutSize < 2 || nLutSize >= 16 )
goto usage;
break;
case 'C':
Expand Down
7 changes: 7 additions & 0 deletions src/base/abci/abcSpeedup.c
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Original file line number Diff line number Diff line change
Expand Up @@ -261,6 +261,11 @@ void Abc_NtkDelayTracePrint( Abc_Ntk_t * pNtk, int fUseLutLib, int fVerbose )
memset( pCounters, 0, sizeof(int)*(nSteps + 1) );
// perform delay trace
tArrival = Abc_NtkDelayTraceLut( pNtk, fUseLutLib );
if ( tArrival == -ABC_INFINITY )
{
ABC_FREE( pCounters );
return;
}
tDelta = tArrival / nSteps;
// count how many nodes have slack in the corresponding intervals
Abc_NtkForEachNode( pNtk, pNode, i )
Expand Down Expand Up @@ -519,6 +524,8 @@ Abc_Ntk_t * Abc_NtkSpeedup( Abc_Ntk_t * pNtk, int fUseLutLib, int Percentage, in
unsigned * puTCEdges;
// perform delay trace
tArrival = Abc_NtkDelayTraceLut( pNtk, fUseLutLib );
if ( tArrival == -ABC_INFINITY )
return NULL;
tDelta = fUseLutLib ? tArrival*Percentage/100.0 : 1.0;
if ( fVerbose )
{
Expand Down
4 changes: 2 additions & 2 deletions src/base/io/ioWriteVerilog.c
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Expand Up @@ -122,7 +122,7 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk, int fOnlyAnds, int fNew
// fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) );
fprintf( pFile, "module %s ( ", Io_WriteVerilogGetName(Abc_NtkName(pNtk)) );
// add the clock signal if it does not exist
if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByNameTwoTypes(pNtk->pManName, "clock", ABC_OBJ_PI, ABC_OBJ_NET) == -1 )
fprintf( pFile, "clock, " );
// write other primary inputs
fprintf( pFile, "\n " );
Expand All @@ -135,7 +135,7 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk, int fOnlyAnds, int fNew
Io_WriteVerilogPos( pFile, pNtk, 3, fNewInterface );
fprintf( pFile, " );\n" );
// add the clock signal if it does not exist
if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByNameTwoTypes(pNtk->pManName, "clock", ABC_OBJ_PI, ABC_OBJ_NET) == -1 )
fprintf( pFile, " input clock;\n" );
// write inputs, outputs, registers, and wires
if ( Abc_NtkPiNum(pNtk) > 0 )
Expand Down
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