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atomic: multi-backend framework + builtin + API rename - #19867

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zhangyu-duck:pr2-atomic-backend
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atomic: multi-backend framework + builtin + API rename#19867
zhangyu-duck wants to merge 9 commits into
apache:masterfrom
zhangyu-duck:pr2-atomic-backend

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@zhangyu-duck zhangyu-duck commented Aug 16, 2026

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Summary

Rework the atomic implementation to support multiple selectable backends via Kconfig:

  • LIBC_ATOMIC_TOOLCHAIN - compiler builtins (default, lock-free)
  • LIBC_ATOMIC_ARCH - arch-native atomic instructions (lock-free)
  • LIBC_ATOMIC_HWSPINLOCK - hardware spinlock wrapping critical section (cross-core)
  • LIBC_ATOMIC_IRQ - IRQ disable wrapping critical section (single-core fallback)

Switch <nuttx/atomic.h> to call toolchain builtin atomic functions directly (__atomic_* / __c11_atomic_* / _Interlocked*), avoiding conflicts with third-party C/C++ standard libraries.

Rename atomic_fetch_xxx -> atomic_xxx (e.g., atomic_fetch_add -> atomic_add) because the atomic_fetch_xxx naming is reserved by the C/C++ standard and conflicts with standard library declarations.

Use _Atomic qualifier for atomic_t typedef when supported, with a __Atomic(t) wrapper for clang/C++ compatibility.

Breaking change

This is a breaking API change. A companion PR in the apps tree renames call sites (atomic_fetch_add -> atomic_add, etc.).

depends-on: apache/nuttx-apps/pull/3733

Stacked PR chain

Depends on #19866. This is PR 2 of 3:

Test

CI testbuild across ARM/RISC-V/SIM targets.

@github-actions github-actions Bot added Arch: arm Issues related to ARM (32-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: sparc Issues related to the SPARC architecture Arch: xtensa Issues related to the Xtensa architecture Area: OS Components OS Components issues Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. labels Aug 16, 2026
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MemBrowse Memory Report

rx65n-rsk2mb

  • ROM: .text +80 B (+0.1%, 87,408 B / 2,097,152 B, total: 4% used)

s698pm-dkit

@github-actions github-actions Bot added the Arch: renesas Issues related to the Renesas chips label Aug 17, 2026
@zhangyu-duck zhangyu-duck reopened this Aug 18, 2026
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zhangyu-duck force-pushed the pr2-atomic-backend branch 4 times, most recently from 4175fc5 to 469409e Compare August 18, 2026 11:40
@github-actions github-actions Bot added Area: Drivers Drivers issues and removed Area: OS Components OS Components issues labels Aug 18, 2026
@github-actions github-actions Bot added Area: Bluetooth Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: simulator Issues related to the SIMulator Board: arm and removed Area: Drivers Drivers issues labels Aug 19, 2026
@zhangyu-duck zhangyu-duck changed the title atomic: multi-backend implementation (IRQ + hwspinlock + arch) atomic: multi-backend framework + builtin + API rename Aug 19, 2026
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zhangyu-duck marked this pull request as ready for review August 19, 2026 06:35
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🔗 Cross-repo PR dependencies

The read-only Build run reported the following dependent PR(s) and fetched head SHA(s):

CI run: https://github.com/apache/nuttx/actions/runs/32223697536

@jerpelea

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Contributor

breaking change commits and PR must me preceded by !
ex:
! nuttx/atomic: use toolchain builtin atomic function

The atomic implementation of machine/arch_atomic.c is achieved by
switching interrupts. This version does not support SMP.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Tricore gcc does not support atomic interface but some users need to
use atomic operations, so support atomic function using tricore arch
instructions (__cmpAndSwap/__swap/__ld32).

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Refine the atomic Kconfig to support multiple backends:
LIBC_ATOMIC_TOOLCHAIN (compiler builtins), LIBC_ATOMIC_ARCH (arch
instructions), and LIBC_ATOMIC_IRQ (interrupt disable). Rename
arch_atomic.c to arch_atomic_irq.c since it supports the IRQ backend.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Select LIBC_ATOMIC_IRQ at the architecture level (ARM7TDMI, ARM926EJS,
ARMv6M) for chips that do not support atomic operations natively. This
covers all ARM7TDMI, ARM926EJS, and Cortex-M0 based chips automatically.

Also select LIBC_ATOMIC_IRQ for specific non-ARM architectures (AVR,
RISC-V, SPARC, Xtensa) that lack atomic instruction support.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Replace atomic_load with atomic_read in call sites to use the
unified interface defined in <nuttx/atomic.h>.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
1. for tasking, map __c11_atomic_xxx as tasking_atomic_xxx
2. for msvc, map  _Interlocked_xxx as msvc_atomic_xxx
3. if no special map, use gcc/clang as default as they are most widely used.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
The reason for using builtin atomic is that in C++, when include <atomic> in <nuttx/atomic.h> easily conflicts with third-party function libraries. We wanted to completely separate the implementation of <nuttx/atomic.h>.

There are two points:
1. use builtin function directly.
2. Without the standard library implementation, need implement "atomic_fetch_xxx", leading conflicts with the standard library used by third-party programs, introducing redefinition issues and requiring name changes.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Rename atomic_fetch_add/sub/or/and/xor to atomic_add/sub/or/and/xor
to avoid conflicts with the C/C++ standard library naming. The
atomic_fetch_xxx naming is reserved by the standard; keeping it causes
function name conflicts when source files indirectly include both
<nuttx/atomic.h> and <atomic>/<stdatomic.h>.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
1. use _atomic as wrapper because if _Atomic empty, may affects the compilation of other files:

2. for clang builtin function, it donot accept param with keyword "_Atomic"

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
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🔗 Cross-repo PR dependencies

The read-only Build run reported the following dependent PR(s) and fetched head SHA(s):

CI run: https://github.com/apache/nuttx/actions/runs/32266949770

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Labels

Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: renesas Issues related to the Renesas chips Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: xtensa Issues related to the Xtensa architecture Area: Bluetooth Board: arm Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.

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3 participants