Route all 47 AM3352 signals with the public bus_lanes phase - #4237
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* docs: plan integrated dogbones and constrained bus lane routing * docs: specify standalone dogbone fanout and local via handoffs * Route all 47 AM3352 signals with the public bus_lanes phase (#4237) * Integrate bus lane pipeline and add original-pad AM3352 regression * Update bus lanes solver to preserve existing fanout handoffs * Gate AM3352 bus lanes on reference routing quality * Verify all 47 AM3352 routes and snapshot each signal layer * Install built bus-lanes props preview consistently in CI * Run dense AM3352 snapshots in a dedicated ARM job * Use portable bus lane solver and restore AM3352 to x86 CI * Use released bus lanes solver from jscdn * Fix portable bus routing and remove the ARM-only snapshot job (#4259) * Use portable bus lane solver and restore AM3352 to x86 CI * Use released bus lanes solver from jscdn * Avoid idle component rendering while asynchronous routing runs * Publish a core preview for end-to-end SVG performance validation * Resolve the preview solver before installing dependencies * Validate compact route quality and refresh the optimized solver preview * Use released solver and connectivity packages in AM3352 integration * Automatically dogbone only unrouted pads without a new prop * Align preview build with the tested Bun 1.4 runtime
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The original AM3352/RAM board now routes all 47 signals with zero native DRC errors through the public phase:
The fixture preserves the reference TSX's footprints, placement, 47 connections, two byte buses, three differential pairs, and timing constraints. It contains no custom algorithm or saved route plan. Automatic dogbones apply only to untouched component pads; existing fanout handoffs stay fixed.
Start review with
tests/features/autorouter-bus-lanes-am3352.test.tsxand its three signal-layer SVG snapshots. Every snapshot is written only after these gates pass:The source-bus assertion includes both byte buses and all three exported differential-pair memberships. The snapshot views explicitly select inner1, inner2, and bottom so the carrier routing is visible. No partial/unrouted AM3352 artifacts are included.
Validation: fresh TSX integration run passed in 281 seconds with 169 assertions; six smaller bus_lanes integration tests and core typecheck pass. The test timeout is 900 seconds for this dense regression. The solver has 49 passing tests and four passing DDR benchmarks; see solver #3.
Dependencies: props uses the built, commit-pinned PR preview from props #875 in both devDependencies and overrides. Replace this preview with its npm release before merge. The dist build and smoke test pass from a clean CI install. The dense AM3352 test has a dedicated Ubuntu ARM job matching the snapshot-update runner, with all 169 assertions and zero image-diff tolerance. Other tests continue in the ten x86 shards. ARM and x86 can select different valid control paths due to floating-point geometry differences. The tested solver is pinned to
de425372f6413e024010d24b64341d64c83a6a12, which uses fanout-solver #252. This PR is stacked on planning #4232.CI is green on
fa67b539ed24f804820a4e8af5172d5b81a9bf92: all ten x86 test shards, the dedicated AM3352 ARM routing/snapshot job (169 assertions), dist build/smoke test, and Vercel preview pass. Test run. No routing assertions, DRC gates, image tolerances, or snapshot geometry were weakened or changed.