Gate x86 SIMD detection by target architecture ## Summary - recognize riscv32 / riscv64 explicitly in Fastor's architecture detection; - keep riscv64 on the existing scalar SIMDVector backend instead of inheriting host x86 SIMD macros.

[carlosqwqqwq]

Why

Fastor already has a scalar SIMDVector fallback, but its SIMD configuration logic currently derives SSE, AVX, AVX512, and FMA support directly from host compiler macros. In simulated or cross-target riscv64 builds this leaks host x86_64 SIMD state into the target configuration and prevents the existing scalar fallback from being selected.

What changed

• Add explicit architecture detection in Fastor/config/config.h for riscv32, riscv64, and x86 targets.
• Restrict the existing x86 intrinsic feature probing so FASTOR_MIC_IMPL, FASTOR_SSE*, FASTOR_AVX*, and FASTOR_FMA* macros are only derived on x86 targets.
• Preserve the existing scalar fallback by allowing non-x86 targets, including riscv64, to reach FASTOR_SCALAR_IMPL.
• Update README.md to document that riscv64 currently uses Fastor's scalar SIMDVector backend unless a dedicated RISC-V backend is added.

Verification

• Ran native CMake configuration with testing disabled for the header-only package:
  • cmake -S . -B build-native-min -G Ninja -DBUILD_TESTING=OFF
• Ran the native build successfully:
  • cmake --build build-native-min --parallel 4
• Ran the native install successfully and verified the exported headers and CMake package files were produced:
  • cmake --install build-native-min --prefix build-native-min\install
• Preprocessed Fastor/config/config.h with forced __riscv=1 and __riscv_xlen=64 and confirmed the result defines FASTOR_ARCH_RISCV, FASTOR_ARCH_RISCV64, and FASTOR_SCALAR_IMPL, without defining FASTOR_SSE2_IMPL or FASTOR_AVX_IMPL.
• Compiled a forced-riscv64 smoke translation unit including Fastor/Fastor.h and confirmed Fastor::choose_best_simd_vector_t<float> resolves to the scalar ABI with Size == 1.
• Preprocessed the same configuration header on the native x86_64 host and confirmed the existing x86 path still defines FASTOR_ARCH_X86 and FASTOR_SSE2_IMPL.
• Verified real riscv64 cross-compilation and execution in Docker (ubuntu:24.04):
  • built a minimal consumer using Tensor<float,2,2> and matmul(...) with host g++;
  • rebuilt the same consumer with riscv64-linux-gnu-g++;
  • confirmed the resulting binary is ELF64 / Machine: RISC-V via file and readelf -h;
  • ran the riscv64 binary successfully with qemu-riscv64-static -L /usr/riscv64-linux-gnu.

Notes

This is a conservative portability patch. It does not add RVV or any other RISC-V SIMD backend. The goal is to make riscv64 use Fastor's existing scalar backend correctly and to stop host x86 SIMD macros from leaking into target selection.