feat: support for Zbb, Zba and Zbs extensions by mansur20478 · Pull Request #3083 · openvm-org/openvm

mansur20478 · 2026-07-29T19:16:36Z

This PR adds support for zbb, zba and zbs extensions. The PR is intended for benchmarking purposes only.

Benchmark results
Baseline: https://github.com/axiom-crypto/openvm-eth/actions/runs/30566664481
With basic bit manipulation extension (per iterative improvement):

Resolves INT-8922

The shadd/slli_uw GPU test harnesses gave the trace-comparison CPU chip the hybrid cpu_range_checker(), whose counts merge into the GPU range checker trace on top of the kernel's own counts, so receives were twice the AIR sends (LogUp NonzeroRootSum). Use a dummy range checker for the CPU comparison chip, matching the add_sub CUDA test idiom.

Mirrors cargo-openvm's env passthrough so benchmark ELFs can be built with -C target-feature=+zba,+zbb,+zbs for bitmanip A/B runs.

ANDN/ORN/XNOR move to a dedicated byte-limb chip that reuses the bitwise XOR lookup (complement folded linearly into the relation), and MIN/MINU/MAX/MAXU move to a less_than-style limb comparison chip with a pick_b selector, writing the selected operand as an expression. Both replace the 348-column reg catch-all rows (27 and 21 core columns respectively) for these seven opcodes; the catch-all keeps serving the rotate and single-bit families until they are extracted too. Executor registration order now matters and matches the AIR/chip order (chips pair with executors positionally); the initial mis-ordering corrupted adapter records in the full-config integration test.

bitmanip/rotate.rs and bitmanip/rotate_imm.rs hold the finished generic rotate cores (ROL/ROR at 4 limbs, ROLW/RORW at 2 limbs behind the W adapter, plus the RORI/RORIW immediate variant with the shamt bound as width*(is_valid - is_idx_zero) - idx). They are intentionally NOT in the module tree yet: wiring (predicates, executors, registration, CUDA, tests) lands with the rotate extraction commit.

Constant propagation can fold a min/max operand to a literal 0, and the inline unsigned ternary then contains 'x < 0ull', which clang rejects under -Werror=tautological-unsigned-zero-compare. Route the four ops through always_inline helpers in rv64b.h so the generated call sites are insensitive to operand shape, and re-seed x10 to zero in the rvr golden program so the folded-zero path stays covered.

REV8 and SEXT.B are the hottest non-shadd B ops on reth (1.6M and 0.95M rows) and were paying the imm catch-all's 310 columns and 5,949 constraints per row. They move (with SEXT.H/ZEXT.H/ORC.B) to a dedicated byte-limb chip whose written value is an expression over the operand bytes: REV8 is pure wiring, ORC.B uses the inverse trick per byte, and the sign extensions decompose the extended byte as lo + 128*t with the low part range checked through the bitwise lookup (2*lo < 256). 27 core columns, ~20 constraints.

github-actions · 2026-07-30T18:16:55Z

group	app.proof_time_ms	app.cycles	leaf.proof_time_ms
fibonacci	459	4,000,051	241
keccak	7,222	14,365,133	1,529
sha2_bench	4,731	11,167,961	527
regex	652	4,090,656	218
ecrecover	231	112,210	183
pairing	288	592,827	184
kitchen_sink	2,629	1,979,971	459

Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights.

Commit: 409a26f

Benchmark Workflow

mansur20478 added 3 commits July 29, 2026 14:06

feat: add RV64 bitmanip (Zba/Zbb/Zbs) support

ef757a9

feat: add rvr support for RV64 bitmanip

29f2525

test: add RV64B guest target-feature test

9b297d7