Add SM100 fused linear SwiGLU

[justinhh4]

Summary

Adds a unified CuTe DSL SwiGLU implementation on top of the current main
SM100 GEMM:

• a differentiable elementwise forward/backward replacement for
  LigerSiLUMulFunction;
• an exact-SM100 fused-linear forward path that computes gate and up projections
  in one grouped GEMM and applies SwiGLU in the epilogue without materializing
  either projection;
• safe fallback to two linear projections plus the elementwise CuTe DSL kernel
  for unsupported architectures, dtypes, and K alignment.

This PR is rebased directly onto main; the former dependency on #1339 has
been removed.

Implementation

• pack_swiglu_weights interleaves gate/up weights in 32-row tiles so paired
  accumulator fragments are local to the same SM100 CTA.
• The grouped custom-epilogue mode is integrated into the current reusable
  _sm100_gemm.py without restoring the retired FLCE row-reduction paths.
• The existing single-fragment FLCE configuration remains unchanged.
• Native fused execution requires exact compute capability (10, 0),
  FP16/BF16 operands, and K divisible by 64.
• Unsupported inputs unpack the weights and run two
  torch.nn.functional.linear calls followed by the CuTe DSL elementwise
  kernel.
• Elementwise and fused kernels launch under the input tensor's CUDA device
  guard and on PyTorch's active CUDA stream for both TVM-FFI and DLPack calling
  paths.

B200 optimization

NCU at M=8192, H=4096, N=14336 classified the grouped kernel as
compute-bound:

• compute throughput: 96.07%
• memory throughput: 62.11%
• registers/thread: 96
• dynamic shared memory/block: 213.25 KiB
• achieved occupancy: 8.63%

A manual pipeline-stage/swizzle sweep selected:

• five A/B stages at 1K tokens;
• six stages from 2K through 16K;
• four stages with the existing eight-way swizzle from 32K upward.

The large-M specialization raises normalized speedup from 1.015x/0.981x
at 32K/64K to 1.053x/1.052x.

BF16 benchmarks

NVIDIA B200, H=4096, N=14336, seven warmups, 21 interleaved samples.
Weight packing is excluded from latency. Peak memory is measured in isolated
provider processes and includes input, one weight representation, output, and
temporary PyTorch CUDA allocations.

Tokens	Two GEMMs + SwiGLU (ms)	Fused SwiGLU (ms)	Speedup	Baseline peak (MiB)	Fused peak (MiB)	Memory ratio
1,024	0.214208	0.223136	0.960x	348	260	1.34x
2,048	0.355776	0.356896	0.997x	440	296	1.49x
4,096	0.691104	0.647360	1.068x	624	368	1.70x
8,192	1.285664	1.217984	1.056x	992	512	1.94x
16,384	2.565120	2.412224	1.063x	1,728	800	2.16x
32,768	5.130048	4.873984	1.053x	3,200	1,376	2.33x
65,536	10.174336	9.672512	1.052x	6,144	2,528	2.43x

Correctness

• CuTe DSL SwiGLU, upstream elementwise SwiGLU, SM100 GEMM, and FLCE regression
  suites: 301 passed, 1 skipped
• Current-stream coverage: elementwise forward, elementwise backward, and
  fused-linear forward
• FP16/BF16 fused correctness, padded output tails, exact-SM100 dispatch, FP32
  fallback, arbitrary elementwise shapes, multipliers, and PyTorch/Triton parity
• make checkstyle: passed

Validation environment:

• NVIDIA B200, SM100, driver 580.105.08
• PyTorch 2.13.0.1+cu130
• Triton 3.7.1
• nvidia-cutlass-dsl 4.6.0
• apache-tvm-ffi 0.1.12

Scope

• src/liger_kernel/ops/cutedsl/ops/swiglu.py
• src/liger_kernel/ops/cutedsl/ops/_sm100_gemm.py
• test/transformers/test_swiglu_cutedsl.py