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Computer-Architecture-Project1

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Group Projects for NTU CSIE Computer Architecture Class

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Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
ALU.v		ALU.v
ALU_Control.v		ALU_Control.v
Adder.v		Adder.v
Branch_And.v		Branch_And.v
CPU.v		CPU.v
Control.v		Control.v
Data_Memory.v		Data_Memory.v
Equal.v		Equal.v
Fibonacci_instruction.txt		Fibonacci_instruction.txt
Fibonacci_output.txt		Fibonacci_output.txt
Forwarding_Unit.v		Forwarding_Unit.v
Hazard_Detection_Unit.v		Hazard_Detection_Unit.v
IF_ID_Flush.v		IF_ID_Flush.v
Instruction_Memory.v		Instruction_Memory.v
Makefile		Makefile
Mem_Stage_tmp.v		Mem_Stage_tmp.v
Mux32.v		Mux32.v
Mux32_3.v		Mux32_3.v
Mux5.v		Mux5.v
MuxControl.v		MuxControl.v
PC.v		PC.v
Pipe_EX_MEM.v		Pipe_EX_MEM.v
Pipe_ID_EX.v		Pipe_ID_EX.v
Pipe_IF_ID.v		Pipe_IF_ID.v
Pipe_MEM_WB.v		Pipe_MEM_WB.v
Registers.v		Registers.v
ShiftLeft2.v		ShiftLeft2.v
Sign_Extend.v		Sign_Extend.v
instruction.txt		instruction.txt
output_answer.txt		output_answer.txt
output_hw4.txt		output_hw4.txt
testbench.v		testbench.v
testbench_hw4.v		testbench_hw4.v

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Group Projects for NTU CSIE Computer Architecture Class

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