atomic: hwspinlock backend for cxd56, rp2040, lc823450

arch/arm/Kconfig

@@ -843,7 +843,6 @@ config ARCH_CHIP_CXD56XX
 	select ARCH_HAVE_MATH_H
 	select ARCH_HAVE_I2CRESET
 	select ARCH_HAVE_CUSTOM_TESTSET
-	select LIBC_ARCH_ATOMIC if SMP
 	---help---
 		Sony CXD56XX (ARM Cortex-M4) architectures
 
@@ -935,15 +934,14 @@ config ARCH_CHIP_CXD32XX
 	bool "Sony CXD32xx"
 	select ARCH_CORTEXM4
 	select ARCH_HAVE_FPU
-	select LIBC_ARCH_ATOMIC
+	select LIBC_ATOMIC_IRQ
 	---help---
 		Sony CXD32XX (ARM Cortex-M4) architectures
 
 config ARCH_CHIP_HT32F491X3
 	bool "Holtek HT32F491x3"
 	select ARCH_CORTEXM4
 	select ARCH_HAVE_FPU
-	select LIBC_ARCH_ATOMIC
 	---help---
 		Holtek HT32F491x3 (ARM Cortex-M4) architectures
 
@@ -967,6 +965,7 @@ config ARCH_ARM7TDMI
 	default n
 	select ARCH_DCACHE
 	select ARCH_ICACHE
+	select LIBC_ATOMIC_IRQ
 	---help---
 		The Arm7TDMI-S is an excellent workhorse processor capable of a wide
 		array of applications. Traditionally used in mobile handsets, the
@@ -996,6 +995,7 @@ config ARCH_ARM926EJS
 	select ARCH_ICACHE
 	select ARCH_HAVE_MMU
 	select ARCH_USE_MMU
+	select LIBC_ATOMIC_IRQ
 	---help---
 		Arm926EJ-S is the entry point processor capable of supporting full
 		Operating Systems including Linux, WindowsCE, and Symbian.
@@ -1051,6 +1051,7 @@ config ARCH_ARMV6M
 	bool
 	default n
 	select ARCH_HAVE_CPUINFO
+	select LIBC_ATOMIC_IRQ
 
 config ARCH_CORTEXM0
 	bool

arch/arm/src/armv7-a/arm_gicv2.c

@@ -72,7 +72,7 @@ static atomic_t g_gic_init_done;
 #if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1
 static void arm_gic_init_done(void)
 {
-  atomic_fetch_or(&g_gic_init_done, 1 << this_cpu());
+  atomic_or(&g_gic_init_done, 1 << this_cpu());
 }
 
 static void arm_gic_wait_done(cpu_set_t cpuset)

arch/arm/src/cxd56xx/CMakeLists.txt

@@ -39,7 +39,9 @@ set(SRCS
     cxd56_icc.c
     cxd56_powermgr.c
     cxd56_farapi.c
-    cxd56_sysctl.c)
+    cxd56_sysctl.c
+    cxd56_hwspinlock.c
+    cxd56_atomic.c)
 
 if(CONFIG_SMP)
   list(APPEND SRCS cxd56_cpuidlestack.c)

arch/arm/src/cxd56xx/Kconfig

@@ -1429,6 +1429,12 @@ config CXD56_TESTSET_WITH_HWSEM
 
 endif # CXD56_TESTSET
 
+config CXD56_ATOMIC_WITH_HWSEM
+	bool "Use atomic based on hardware semaphore"
+	default !CXD56_USE_SYSBUS
+	depends on SMP
+	select LIBC_ATOMIC_HWSPINLOCK
+
 config CXD56_USE_SYSBUS
 	bool "Use the system bus for the data section"
 	default y

arch/arm/src/cxd56xx/Make.defs

@@ -39,6 +39,8 @@ CHIP_CSRCS += cxd56_icc.c
 CHIP_CSRCS += cxd56_powermgr.c
 CHIP_CSRCS += cxd56_farapi.c
 CHIP_CSRCS += cxd56_sysctl.c
+CHIP_CSRCS += cxd56_atomic.c
+CHIP_CSRCS += cxd56_hwspinlock.c
 
 ifeq ($(CONFIG_SMP),y)
 CHIP_CSRCS += cxd56_cpuidlestack.c

arch/arm/src/cxd56xx/cxd56_atomic.c

@@ -0,0 +1,50 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_atomic.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/hwspinlock/hwspinlock.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define SPH_SMP  13
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern const struct hwspinlock_ops_s g_cxd56_hwspinlock_ops;
+
+struct hwspinlock_dev_s g_atomic_hwspinlock =
+{
+  .id       = SPH_SMP,
+  .priority = 0,
+  .ops      = &g_cxd56_hwspinlock_ops
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/

arch/arm/src/cxd56xx/cxd56_hwspinlock.c

@@ -0,0 +1,63 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_hwspinlock.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/hwspinlock/hwspinlock.h>
+
+#include "arm_internal.h"
+#include "hardware/cxd56_sph.h"
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static bool cxd56_hwspinlock_trylock(struct hwspinlock_dev_s *dev);
+static void cxd56_hwspinlock_unlock(struct hwspinlock_dev_s *dev);
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+const struct hwspinlock_ops_s g_cxd56_hwspinlock_ops =
+{
+  .trylock = cxd56_hwspinlock_trylock,
+  .unlock  = cxd56_hwspinlock_unlock
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static bool cxd56_hwspinlock_trylock(struct hwspinlock_dev_s *dev)
+{
+  uint32_t sphlocked = ((up_cpu_index() + 2) << 16) | 0x1;
+
+  putreg32(REQ_LOCK, CXD56_SPH_REQ(dev->id));
+
+  return getreg32(CXD56_SPH_STS(dev->id)) == sphlocked;
+}
+
+static void cxd56_hwspinlock_unlock(struct hwspinlock_dev_s *dev)
+{
+  putreg32(REQ_UNLOCK, CXD56_SPH_REQ(dev->id));
+}

arch/arm/src/cxd56xx/cxd56_sph.c

@@ -270,9 +270,11 @@ int cxd56_sphinitialize(const char *devname)
   int ret;
   int i;
 
-  /* No. 0-2 and (14)-15 semaphores are reserved by other system. */
+  /* No. 0-2 and (13)-15 semaphores are reserved by other system. */
 
-#ifdef CONFIG_CXD56_TESTSET
+#if defined(CONFIG_CXD56_ATOMIC_WITH_HWSEM)
+  for (i = 3; i < 13; i++)
+#elif defined(CONFIG_CXD56_TESTSET_WITH_HWSEM)
   for (i = 3; i < 14; i++)
 #else
   for (i = 3; i < 15; i++)

arch/arm/src/lc823450/Make.defs

@@ -25,6 +25,7 @@ include armv7-m/Make.defs
 CHIP_CSRCS  = lc823450_allocateheap2.c lc823450_start.c lc823450_irq.c lc823450_timer.c
 CHIP_CSRCS += lc823450_lowputc.c lc823450_serial.c lc823450_clockconfig.c
 CHIP_CSRCS += lc823450_syscontrol.c lc823450_gpio.c
+CHIP_CSRCS += lc823450_hwspinlock.c
 
 # Configuration-dependent LC823450 files
 
@@ -123,3 +124,4 @@ endif
 ifeq ($(CONFIG_ARM_MPU),y)
 CHIP_CSRCS += lc823450_mpuinit2.c
 endif
+CHIP_CSRCS += lc823450_atomic.c

arch/arm/src/lc823450/lc823450_atomic.c

@@ -0,0 +1,50 @@
+/****************************************************************************
+ * arch/arm/src/lc823450/lc823450_atomic.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/hwspinlock/hwspinlock.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define LC823450_MUTEX_REG  0
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern const struct hwspinlock_ops_s g_lc823450_hwspinlock_ops;
+
+struct hwspinlock_dev_s g_atomic_hwspinlock =
+{
+  .id       = LC823450_MUTEX_REG,
+  .priority = 0,
+  .ops      = &g_lc823450_hwspinlock_ops
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/

arch/arm/src/lc823450/lc823450_hwspinlock.c

@@ -0,0 +1,78 @@
+/****************************************************************************
+ * arch/arm/src/lc823450/lc823450_hwspinlock.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/hwspinlock/hwspinlock.h>
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define LC823450_MUTEX_REG_BASE  0x40005000
+
+/* Public datasheet not find and assume reg address continuous and length 4 */
+
+#define LC823450_MUTEX_REG_LEN  4
+#define LC823450_MUTEX_REG_ADDR(id) \
+  (LC823450_MUTEX_REG_BASE + (id) * LC823450_MUTEX_REG_LEN)
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static bool lc823450_hwspinlock_trylock(struct hwspinlock_dev_s *dev);
+static void lc823450_hwspinlock_unlock(struct hwspinlock_dev_s *dev);
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+const struct hwspinlock_ops_s g_lc823450_hwspinlock_ops =
+{
+  .trylock = lc823450_hwspinlock_trylock,
+  .unlock  = lc823450_hwspinlock_unlock
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static bool lc823450_hwspinlock_trylock(struct hwspinlock_dev_s *dev)
+{
+  uint32_t val;
+
+  val = (up_cpu_index() << 16) | 0x1;
+  putreg32(val, LC823450_MUTEX_REG_ADDR(dev->id));
+
+  return getreg32(LC823450_MUTEX_REG_ADDR(dev->id)) == val;
+}
+
+static void lc823450_hwspinlock_unlock(struct hwspinlock_dev_s *dev)
+{
+  uint32_t val;
+
+  val = (up_cpu_index() << 16) | 0x0;
+  putreg32(val, LC823450_MUTEX_REG_ADDR(dev->id));
+}

arch/arm/src/rp2040/Make.defs

@@ -35,6 +35,7 @@ CHIP_CSRCS += rp2040_pio.c
 CHIP_CSRCS += rp2040_clock.c
 CHIP_CSRCS += rp2040_xosc.c
 CHIP_CSRCS += rp2040_pll.c
+CHIP_CSRCS += rp2040_hwspinlock.c
 
 ifeq ($(CONFIG_SMP),y)
 CHIP_CSRCS += rp2040_cpustart.c
@@ -103,3 +104,4 @@ ifneq ($(PICO_SDK_PATH),)
 include chip/boot2/Make.defs
 endif
 endif
+CHIP_CSRCS += rp2040_atomic.c