Skip to content

fix[STM32][SPI]: ignore benign Tx-only OVR after async completion

e22cb69
Select commit
Loading
Failed to load commit list.
Sign in for the full log view
Open

feat[STM32][SPI]: add interrupt transfer mode support #11368

fix[STM32][SPI]: ignore benign Tx-only OVR after async completion
e22cb69
Select commit
Loading
Failed to load commit list.

Annotations

1 warning
assign-reviewers
succeeded May 11, 2026 in 12s