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Add SCTLR bitfield definition for Cortex-R - #317

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hamtinepeng:sctlr-armv8r
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Add SCTLR bitfield definition for Cortex-R#317
hamtinepeng wants to merge 1 commit into
ARM-software:mainfrom
hamtinepeng:sctlr-armv8r

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@hamtinepeng

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Add System Control Register (SCTLR) bitfield definitions for the ARMv8-R architecture, based on the Cortex-R52 Technical Reference Manual.

Add System Control Register (SCTLR) bitfield definitions for the
ARMv8-R architecture, based on the Cortex-R52 Technical Reference
Manual.

Signed-off-by: Romain Mahoux <romain@mahoux.fr>
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github-actions Bot commented Sep 2, 2026

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Test Results

   256 files   -    388     256 suites   - 388   0s ⏱️ - 10m 58s
    56 tests +     7      54 ✅ +   10      2 💤  -     3  0 ❌ ±0 
13 860 runs   - 17 696  11 476 ✅  - 8 680  2 384 💤  - 9 016  0 ❌ ±0 

Results for commit ae4b5a3. ± Comparison against base commit 4fd64d5.

This pull request removes 49 and adds 56 tests. Note that renamed tests count towards both.
CMSIS-Core.src ‑ apsr.c
CMSIS-Core.src ‑ basepri.c
CMSIS-Core.src ‑ bkpt.c
CMSIS-Core.src ‑ clrex.c
CMSIS-Core.src ‑ clz.c
CMSIS-Core.src ‑ control.c
CMSIS-Core.src ‑ cp15.c
CMSIS-Core.src ‑ cpsr.c
CMSIS-Core.src ‑ dmb.c
CMSIS-Core.src ‑ dsb.c
…
TC_CML1Cache_CleanDCacheByAddrWhileDisabled
TC_CML1Cache_EnDisableDCache
TC_CML1Cache_EnDisableICache
TC_CoreFunc_APSR
TC_CoreFunc_BASEPRI
TC_CoreFunc_Control
TC_CoreFunc_EnDisIRQ
TC_CoreFunc_EncDecIRQPrio
TC_CoreFunc_FAULTMASK
TC_CoreFunc_FPSCR
…
This pull request removes 5 skipped tests and adds 2 skipped tests. Note that renamed tests count towards both.
CMSIS-Core.src ‑ lda.c
CMSIS-Core.src ‑ ldaex.c
CMSIS-Core.src ‑ stl.c
CMSIS-Core.src ‑ stlex.c
CMSIS-Core.src ‑ systick.c
TC_CoreInstr_WFE
TC_CoreInstr_WFI

@JonatanAntoni

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cc @Masmiseim36

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🟢 Approval recommended

The change is a straightforward addition of bitfield macros consistent with existing CMSIS headers and introduces no behavioral logic changes.

Pull request overview

Adds missing System Control Register (SCTLR) bit position/mask macros for the ARMv8‑R (Cortex‑R) profile header, aligning armv8r.h with the existing CMSIS pattern used in other profiles (e.g., armv7r.h, armv8a.h) so consumers can manipulate SCTLR fields via named bit definitions.

Changes:

  • Introduces SCTLR_*_Pos and SCTLR_*_Msk macros for key SCTLR fields in CMSIS/Core/Include/r-profile/armv8r.h.
  • Covers enable/configuration bits such as TE/EE/FI/UWXN/WXN and cache/MMU related bits (I/C/A/M), plus additional fields like nTWE, nTWI, and BR.
File summaries
File Description
CMSIS/Core/Include/r-profile/armv8r.h Adds ARMv8‑R SCTLR bit position/mask macros to support clearer, safer SCTLR manipulation in user code.
Review details
  • Files reviewed: 1/1 changed files
  • Comments generated: 0
  • Review effort level: Lite

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3 participants