diff --git a/src/engine/compiler/SinglePassCompiler.v3 b/src/engine/compiler/SinglePassCompiler.v3
index 6733c0c74..aca601973 100644
--- a/src/engine/compiler/SinglePassCompiler.v3
+++ b/src/engine/compiler/SinglePassCompiler.v3
@@ -2127,6 +2127,10 @@ class SinglePassCompiler(xenv: SpcExecEnv, masm: MacroAssembler, regAlloc: RegAl
 		if (Trace.compiler) Trace.OUT.put1("  OSR (+%d)", osr_entry_label.create_pos).ln();
 		masm.bindLabel(osr_entry_label);
 		emit_reload_regs();
+		if (SpcTuning.inlineWhammProbes && SpcTuning.intrinsifyWhammProbe) {
+			// Clear sidetable pointer in this slot
+			masm.emit_mov_m_l(frame.inlined_instance_slot, 0);
+		}
 		for (i < u32.!(state.length)) {
 			var sv = state[i];
 			var iv = SpcVal(sv.kindFlags(IS_STORED | TAG_STORED), NO_REG, 0);
diff --git a/test/wizeng/osr_gc.wasm b/test/wizeng/osr_gc.wasm
new file mode 100644
index 000000000..e640d4031
Binary files /dev/null and b/test/wizeng/osr_gc.wasm differ
diff --git a/test/wizeng/osr_gc.wasm.exit b/test/wizeng/osr_gc.wasm.exit
new file mode 100644
index 000000000..573541ac9
--- /dev/null
+++ b/test/wizeng/osr_gc.wasm.exit
@@ -0,0 +1 @@
+0
diff --git a/test/wizeng/osr_gc.wasm.flags b/test/wizeng/osr_gc.wasm.flags
new file mode 100644
index 000000000..e827cf200
--- /dev/null
+++ b/test/wizeng/osr_gc.wasm.flags
@@ -0,0 +1 @@
+--expose=wizeng
diff --git a/test/wizeng/osr_gc.wat b/test/wizeng/osr_gc.wat
new file mode 100644
index 000000000..884c1c26e
--- /dev/null
+++ b/test/wizeng/osr_gc.wat
@@ -0,0 +1,7 @@
+(module
+  (import "wizeng" "force_gc" (func $gc))
+  (func (export "main") (local $i i32)
+    ;; the loop tiers up while this frame still holds the interpreter's sidetable pointer
+    (loop $l
+      (call $gc)
+      (br_if $l (i32.lt_u (local.tee $i (i32.add (local.get $i) (i32.const 1))) (i32.const 10))))))